An arithmetic unit has two operand registers that latch input data, a result register that latches operation result data, and an arithmetic circuit provided between the operand registers and the result register. In addition, the arithmetic unit has a plurality of the arithmetic circuits disposed in parallel with each other between the operand registers and the result register, and selects the operation result data of the plurality of the arithmetic circuits using a selector; then, the selected operation result data is latched by the result register. Further, the arithmetic unit has a bypass route that supplies the data latched by the result register, to the operand register. A subsequent operation is executed within a shorter time period in the case where the operand register directly latches the operation result data by using the bypass route, as compared to the case where: the operation result data of the result register is written in a register file; the operand register then latches the data written in the register file; and the arithmetic circuit performs the operation.
An adder-subtractor, which is a type of arithmetic unit, has a first XOR circuit (XOR: Exclusive OR) and an adder between operand registers and a result register, the first XOR circuit inverting or non-inverting input data of one of the operand registers. The first XOR circuit inverts the input data in the case where the adder-subtractor executes subtraction, and does not invert the input data in the case where the adder-subtractor executes addition. The adder has a second XOR circuit that performs an XOR operation of the input data of the operand registers, a carry calculation unit that generates carry data from input data, and a third XOR circuit that performs the XOR operation of the output of the second XOR circuit and the output of the carry calculation unit. In addition, the adder-subtractor has a result register that latches the output of the third XOR circuit and a first bypass route that transfers the output of the third XOR circuit to the operand registers.
An adder is disclosed in Japanese Patent Application Laid-open No. 2000-89937. And, an adder-subtractor is disclosed in U.S. Pat. No. 7,313,586B2.
In the adder-subtractor, a delay time from the operand registers to the output of the third XOR circuit corresponds to the limit of a clock cycle (shortest cycle) that is supplied to the operand registers and the result register. That is, a critical path that determines the limit of the clock cycle is a path from the operand registers to the third XOR circuit in the arithmetic circuit.
It has in the prior art been proposed to improve the critical path of the adder-subtractor so as to reduce the delay time described above. For example, such a proposal is disclosed in U.S. Pat. No. 7,313,586B2 described below. This adder-subtractor has the first XOR circuit provided at a stage previous to the operand registers, has, in a second bypass route, a fourth XOR circuit that inverts or non-inverts the output of the second XOR circuit and an additional third XOR circuit that performs the XOR operation of the output of the fourth XOR circuit and the carry output, and supplies the output of the additional third XOR circuit to the operand register via the second bypass route.